Design And Reuse

Nuclei and Lauterbach Successfully Complete World's First RISC-V Data Trace Solution

Hoehenkirchen/Shanghai - Nuclei System Technology, supplier of high performance, low power, and secure RISC V CPU cores, and Lauterbach GmbH, global leader for embedded development tools, officially ...
Electronic Design

Five AI-Based SBCs for Edge Computing and Robotics

These new AI-focused SBCs pair multicore processors with integrated NPUs for edge computing, robotics, and embedded ...
GitHub

JTAG Debug Module for RISC-V SoC

The goal of this project is to design a JTAG-based Debug Module that adheres to the RISC-V Debug Specification, enabling features such as: Halting/resuming core execution Reading and writing CPU ...
IEEE

A Resilient System Design to Boot a RISC-V MPSoC

Abstract: This paper presents a highly resilient boot process design for Ballast, a new RISC- V based multiprocessor system-on-chip (SoC). An open source RISC- V SoC was adapted as a bootstrap ...
Semiconductor Engineering

A Self-Evolving Agent Framework That Treats Hardware Design as Repository-Level Code Evolution (Nvidia Research)

A new technical paper, Agentic Hardware Design as Repository-Level Code Evolution, was published by researchers at Nvidia ...
GitHub

A simple pipelined version of RISC-Compute-Module.

An FSM based processor will only get you so far. Yes its very easy to modify but with such modifications to the core, but it costs you precious cycles and other aspects. In this repository instead of ...